With recent advancement in semiconductor device manufacturing, and in particular with regard to fin-type field-effect-transistors (FinFETs), epitaxially formed source/drain is increasingly becoming preferred and may even be inevitable in order to provide low resistance contacts to the FinFETs and other devices, such as nanowires, that involve the use of epitaxial processes. A merged epitaxy process is typically used in forming epitaxial source/drain for FinFET transistors. However, merged epitaxy process also mandates several ground rules which could potentially lead to area penalties such as loss of real estate in a semiconductor chip. For example, with current FinFET manufacturing technology, dummy fins are generally needed to be strategically placed between every two transistors, and a gate is generally required to extend past fins for a certain length in order to avoid source/drain (S/D) short due to possible epitaxial round-about. In addition, fins need to be tucked under dummy gate in order to avoid extensive epitaxial growth at free ends of the fins.
Several processes have been proposed recently to relax these requirements on ground rules. For example, it has been proposed to oxidize dummy fins as opposed to remove them. However, concerns still remain as to potential oxygen diffusion through the bulk oxide (BOX) and affecting active fins. Another approach is to use shallow trench isolation (STI) that extrudes out. However, the STI made by the above process is not self-aligned to the fins. For example, the width and location of STI is usually defined by a mask, which may not necessarily be aligned with the fins.